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Programmable Penta ULDO with RESET and I2C Interface
POWER MANAGEMENT Description
The SC900A is a highly integrated power management device for low power portable applications. The device contains five adjustable low-dropout linear regulators (LDOs) with CMOS pass-devices as well as a band-gap reference, I2C interface, and DACs to control the output voltages. Many features of the SC900A are programmable through the I2C interface. These include the ability to independently turn on any combination of the five regulators. All five of the LDO output voltages are programmable in 50mV steps from 1.45V to 3.00V for LDOs A and B, and from 1.75V to 3.30V for LDOs C, D and E. Each LDO can have an active shutdown or nonactive shutdown program option through the interface. There is also a reset monitor flag that is associated with LDOA. In addition, the device has a separate programmable power good monitor flag that activates when one or more LDOs go out of regulation. The SC900A offers significant quiescent current and space savings to the system designer by sharing reference and biasing among five LDOs. The small and thermally efficient 20-lead MLPQ package make it ideal for use in portable products where minimizing layout area is critical.
SC900A
Features
Five LDO regulators in one package I2C interface with multiple device capability Independent I2C enable/disable of LDOs Independent I2C control of output voltages Low thermal impedance of 40C per watt 150mV dropout at 150mA Input range from 2.7V to 5.5V Programmable power good flag Minimal number of external components Over temperature protection Small 4mm x 4mm 20-lead MLPQ package Small input/output filter capacitors Programmable VOUT range 1.45V to 3.00V for LDOs A and B 1.75V to 3.30V for LDOs C, D and E
Applications
Palmtop/Laptop computers Personal Digital Assistants Cellular telephones Battery-powered equipment High efficiency linear power supplies
Typical Application Circuit
SC900A
LDOE LDOD LDOA LDOB LDOC
2.2uF
4.7uF
+ - VBAT
VIN INA INB INCD INE EN LDOPGD ARST SDA SCL A0 GND
2.2uF
2.2uF
2.2uF
Baseband Processor
VREF
0.1uF
Receiver Section
LNA
VASEL DGND
Keypad
Audio Processing
TCXO & Synthesiser Transmitter Section
PA
Digital Interface
Camera Processing
2.2uF
CCD
November 14, 2005
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SC900A
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Input Supply Voltage Digital Input Voltage Operating Ambient Temperature Range Operating Junction Temperature Range Peak IR Flow Temperature Storage Temperature Thermal Impedance Junction to Ambient(1) ESD Protection Level(2)
Symbol VIN VDIG TA TJ TLEAD TSTG JA ESD
Maximum -0.3 to +7 -0.3 to VIN +0.3 -40 to +85 -40 to +125 260 -60 to +150 40 2
Units V V C C C C C/W kV
(1) Calculated from package in still air, mounted to 3" x 4.5", 4 layer FR4 PCB with thermal vias under the exposed pad as per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B.
Electrical Characteristics
Unless otherwise noted VIN = 3.7V, TA = -40 to +85C. Typical values are at TA = +25C.
Parameter General Supply Voltage Quiescent Current Shutdown Supply Bypass Capacitor Digital Inputs Digital Input Voltage Digital Input Current Digital Outputs Digital Output Voltage(1)
Symbol
Conditions
Min
Typ
Max
Units
VIN IQ-SHUTDOWN CVCC
All outputs < VIN - dropout
2.7
5.5 10
V A F
Per input pin
1
VIL VIH IDIG 1.6 -0.2
0.4
V V
0.2
A
VOL VOH
ISINK= 1.2mA, V 1.8V ISOURCE = 0.5mA, V 1.8V 90
2 98
10
%LDOB %LDOB
Referencing and Biasing Circuitry Quiescent Current Reference Reference Voltage VREF Start-Up Time VREF Bypass Capacitor
(c) 2005 Semtech Corp.
IQ-REF VREF IVREF CVREF
2
25 1.227 CVREF = 100nF 15 0.1
A V ms F
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SC900A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter LDO Regulators Quiescent Supply Current Quiescent Supply Current at Start-Up Current Limit Bypass Capacitor LDO Regulator A (Core Supply) Output Voltage Accuracy Output Voltage Accuracy at 2.80V (DAC = 11011) Output Voltage Accuracy at 1.80V (DAC = 00011) Output Voltage Accuracy at 2.80V (DAC = 11011) Maximum Output Current Default Setting: ON Line Regulation at 1.8V, 2.8V Load Regulation at 1.8V, 2.8V Dropout Voltage Power Supply Rejection Ratio IOMAXA VOA-HI VOA-LO LINEREGA LOADREGA VDA PSRRA VASEL - High VASEL - Low IOUT = 1mA, VOUT + 0.2V < VIN < 5.5V 1mA < IOUT <200mA VOUT = 3.0V, IOUT = 200mA f = 10Hz - 1kHz, CBYP = 0.1F, IOUT = 50mA, 2.5V VOUT 3.0V f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1F, COUT = 2.2F, 2.5V VOUT 3.0V VOASA VOAA 1.45V VOUT 3.00V VOUT + 0.2V VIN 5.5V IOUT = 1mA, TA = 25C IOUT = 1mA IOUT = 1mA, TA = 25C VOUT + 0.5V VIN 5.5V, IOUT = 200mA -3 -2 -3 -3.5 200 2.80 1.80 2.5 -3 200 60 12 -20 250 +3 +2 +3 +3.5 % % % % mA V V mV mV mV dB IQ IQSUP ILIM CBYP Ceramic, low ESR All LDOs active in default states LDO A, B, C active in default states VOUT + 0.5V < VIN < 5.5V 250 2.2 190 125 410 650 360 A A mA F Symbol Conditions Min Typ Max Units
Output Voltage Noise(2)
en-A
45
VRMS
LDO Regulator B (DIGITAL I/O SUPPLY) Output Voltage Accuracy VOAB 1.45V VOUT 3.00V VOUT + 0.15V VIN 5.5V IOUT = 1mA, TA = 25C IOUT = 1mA VOASB VOUT + 0.5V VIN 5.5V, IOUT = 150mA -3 -2 -3.5 150
3
+3 +2 +3.5
% % % mA
Output Voltage Accuracy at 2.80V (DAC = 11011) Maximum Output Current
(c) 2005 Semtech Corp.
IOMAXB
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SC900A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter Symbol Conditions Min Typ Max Units
LDO Regulator B (DIGITAL I/O SUPPLY) (Cont.) Default Setting: ON Line Regulation at 2.8V Load Regulation at 2.8V Dropout Voltage Power Supply Rejection Ratio VOB LINEREGB LOADREGB VDB PSRRB IOUT = 1mA, VOUT + 0.15V < VIN < 5.5V 1mA < IOUT <150mA VOUT = 3.0V, IOUT = 150mA f = 10Hz - 1kHz, CBYP = 0.1F, IOUT = 50mA, 2.5V VOUT 3.0V f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1F, COUT = 2.2F, 2.5V VOUT 3.0V 2.80 2.5 -3 150 60 12 20 190 mV mV mV mV dB
Output Voltage Noise(2) LDO Regulator C Output Voltage Accuracy
en-B
45
VRMS
VOAC
1.75V VOUT 3.30V VOUT + 0.15V VIN 5.5V IOUT = 1mA, TA = 25C IOUT = 1mA
-3 -2 -3.5 150 2.90
+3 +2 +3.5
% % % mA V
Output Voltage Accuracy at 2.90V (DAC = 10111) Maximum Output Current Default Setting: ON Line Regulation at 2.90V Load Regulation at 2.90V Dropout Voltage Power Supply Rejection Ratio
VOASC IOMAXC VOC LINEREGC LOADREGC VDC PSRRC
VOUT + 0.5V VIN 5.5V, IOUT = 150mA
IOUT = 1mA, VOUT + 0.15V < VIN < 5.5V 1mA < IOUT <150mA VOUT = 3.3V, IOUT = 150mA f = 10Hz - 1kHz, CBYP = 0.1F, IOUT = 50mA, 2.5V VOUT 3.3V f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1F, COUT = 2.2F, 2.5V VOUT 3.3V 1.75V VOUT 3.30V VOUT + 0.15V VIN 5.5V IOUT = 1mA, TA = 25C IOUT = 1mA
2.5 -3 150 60
12 -20 190
mV mV mV dB
Output Voltage Noise(2) LDO Regulator D Output Voltage Accuracy
en-C
55
VRMS
VOAD
-3 -2 -3.5
+3 +2 +3.5
% % %
Output Voltage Accuracy at 3.10V (DAC = 10111)
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VOASD
VOUT + 0.5V VIN 5.5V, IOUT = 150mA
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SC900A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter LDO Regulator D (Cont.) Maximum Output Current Default Setting: OFF Line Regulation at 3.10V Load Regulation at 3.10V Dropout Voltage Power Supply Rejection Ratio IOMAXD VOD LINEREGD LOADREGD VDD PSRRD IOUT = 1mA, VOUT + 0.15V < VIN < 5.5V 1mA < IOUT <150mA VOUT = 3.3V, IOUT = 150mA f = 10Hz - 1kHz, CBYP = 0.1mF, IOUT = 50mA, 2.5V VOUT 3.3V f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1F, COUT = 2.2F, 2.5V VOUT 3.3V 150 3.10 2.5 -3 150 60 12 -20 190 mA V mV mV mV dB Symbol Conditions Min Typ Max Units
Output Voltage Noise(2) LDO Regulator E Output Voltage Accuracy
en-D
55
VRMS
VOAE
1.75V VOUT 3.30V VOUT + 0.15V VIN 5.5V IOUT = 1mA, TA = 25C IOUT = 1mA
-3 -2 -3.5 150 3.10
+3 +2 +3.5
% % % mA V
Output Voltage Accuracy at 3.10V (DAC = 10111) Maximum Output Current Default Setting: OFF Line Regulation at 3.10V Load Regulation at 3.10V Dropout Voltage Power Supply Rejection Ratio
VOASE IOMAXE VOE LINEREGE LOADREGE VDE PSRRE
VOUT + 0.5V VIN 5.5V, IOUT = 150mA
IOUT = 1mA, VOUT + 0.15V < VIN < 5.5V 1mA < IOUT = 150mA VOUT = 3.3V, IOUT = 150mA f = 10Hz - 1kHz, CBYP = 0.1F, IOUT = 50mA, 2.5V VOUT 3.3V f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1F, COUT = 2.2F, 2.5V VOUT 3.3V
2.5 -3 150 60
12 -20 190
mV mV mV dB
Output Voltage Noise(2) A RESET Reset Threshold Reset Active Timeout Delay LDO POWER GOOD PGOOD Threshold PGOOD Active Timeout Delay
en-E
55
VRMS
RESETTHLD tRD PGOODTHLD tPG Delay in default state 75 Delay in default state 75
77 100 77 100 125 125
% ms % ms
Notes: 1) Digital outputs are powered from LDOB, so LDOB must be active for operation of LDOPGD and ARST. 2) Below 2.5V: becomes digital regulator.
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SC900A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter I2C Interface
Interface complies with slave mode I2C interface as described by Philips I2C specification version dated January 2000.
Symbol
Conditions
Min
Typ
Max
Units
Digital Input Voltage SDA Output Low Level Digital Input Current I/O Pin Capacitance I2C Timing Clock Frequency SCL Low Period SCL High Period Data Hold Time Data SetupTime Setup Time for Repeated Start Condition Hold Time for Repeated Start Condition Setup Time for Stop Condition Bus-Free Time Between STOP and START
VIL VIH IDIN (SDA) = 3mA IDIN (SDA) = 6mA IDG CIN -0.2 10 1.6
0.4 0.4 0.6 0.2
V V V V A pF
fSCL tLOW tHIGH THD_DAT TSU_DAT TSU_STA THD_STA TSU_STO tBUF 1.3 0.6 0 100 0.6 0.6 0.6 1.3
400
440
kHz s s s s s s s s
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SC900A
POWER MANAGEMENT Pin Configuration
LDOC LDOD LDOA INCD INA
Ordering information
DEVICE SC900AMLTRT(1)(2)
15
PACKAGE MLPQ20L Evaluation Board
20
19
18
17
16
LDOB INB SDA SCL EN
1 2 3 4 5 6 7 T 8 9 10
LDOE INE VIN GND VREF
SC900AEVB
TOP VIEW
14 13 12 11
Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is WEEE and RoHS compliant.
LDOPGD
DGND
VASEL
MLPQ20: 4X4 20 LEAD
ARST
A0
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SC900A
POWER MANAGEMENT Pin Descriptions
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T Pin Name LDOB INB SDA SCL EN A0 DGND VASEL LDOPGD ARST VREF GND VIN INE LDOE LDOD INCD LDOC INA LDOA Thermal Pad Pin Function LDO B output. Input supply for the digital system logic and the LDO B pass transistor. Bidirectional open drain digital I/O pin. I2C serial data. Digital input. I2C serial clock. Digital input. High to enable part. Low to disable part (sleep mode). Note I2C control is active only when part is enabled. One bit address for connecting two SC900A devices on to the system through the I2C interface. Digital ground. LDO A selection default voltage. Tie this pin to ground for 1.8V or INB for 2.8V. Digital output. State change indicates that one of four LDO output voltages (A, C, D or E) is out of spec. Note, desired state of pin is programmable through the I2C interface. Digital output. State change indicates LDO A output voltage is out of spec. Note, desired state of pin is programmable through the I2C interface. Bandgap reference output voltage. Connect at least 0.1F to ground (CVREF 0.1F). Analog ground. Analog supply voltage. Input supply for the LDO E pass transistor. LDO E output. LDO D output. Input supply for the LDO C and LDO D pass transistors. LDO C output. Input supply for the LDO A pass transistor. LDO A output. Thermal Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.
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SC900A
POWER MANAGEMENT Block Diagram
INA 19 INB INB
2
VIN 13
Reference
11
VREF
DACs EN
5 LDO ref en input out dac
I 2C Interface en VASEL
8
en
DAC A DAC B DAC C DAC D DAC E
20
LDOA
vasel
DAC CNTL
CNTL Input
SCL SDA A0
4 3 6
scl sda a0 LDO CNTL reset CNTL INB Reset/SHDN Control arst reset ldopgd
LDO ref en input out dac
VOB
1
LDOB
LDO ref en input out dac
18 LDOC
VOB ARST 10 LDOPGD
9
LDO ref en input out dac
16
LDOD
LDO ref en input out dac
15
LDOE
INCD 17
INE 14
7
12
DGND
GND
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SC900A
POWER MANAGEMENT Applications Information
General Description Each of the five low-dropout linear regulators (LDOs) can be independently enabled or disabled and their output voltages can each be set by an independent DAC. These controls can be accessed through the I2C serial port. There are five 8-bit volatile registers in the SC900A; one for each LDO (registers A,B,C,D,E). In addition there is one common reset and power good control register and one on/off control register. The active shutdown circuitry can be accessed through each LDO register (refer to the section "Active Shutdown" on page 11 for more information). At power-up, the register contents are reset to their default values and the ARST for LDO A has a default start-up delay of 100ms. At any time the part can be put into it's lowest power state (shutdown) by pulling the EN pin low. Whenever the EN pin is forced low, the previous settings are lost and the part requires reprogramming to return to the desired state. When EN is pulled high, the device starts up in the default state. A detailed description of the protocol used to load the registers with data is described in the section entitled "Using the I2C Interface" on page 14. VIN and Enable Pin The VIN supply must be 2.7V before the EN pin can be asserted. This means that the EN pin should not be tied to VIN so that it does not reach a logic high level before the input supply reaches 2.7V. LDOA (Core Supply) LDOA is intended to be used as the core supply. It has an output current capability of 200mA and a dedicated reset signal ARST. INA is the dedicated input supply for this regulator. LDOB (Digital I/O Supply) INB supplies power for the internal I2C interface and other digital I/O functions, while LDOB supplies power for ARST and LDOPGD output ports (see Block Diagram). Therefore it is imperative that LDOB be operational to make use of ARST and LDOPGD. If LDOB is turned off by the on/off control register, these output ports will not function. LDO RESET Control Register: ARST Pin There are two functions that can be programmed, defining the ARST pin action: * Set the polarity of the reset signal * Set the reset clear delay time in milliseconds As soon as the LDOA output voltage falls below its programmed value, the ARST pin is asserted. The polarity of the ARST pin can be set to active high or active low during a reset condition, by bit 6 of the LDO Reset Control Register. Once the error condition is resolved (output rises to the programmed value), a delay is initiated before the ARST pin is cleared. The delay is programmable by bits 0-1 of the LDO Reset Control Register. The Default delay time is 100ms, and the delay can be programmed for 0, 50, 100, or 150ms. LDOPGD Pin There are three functions that can be programmed to define the LDOPGD pin action: * Set which LDOs are to be monitored for power good * Set the polarity of the power good signal * Set the power good delay time in milliseconds Bits 4 and 5 of the LDO Reset Control Register select which LDO or LDOs are monitored. LDO C, D and E can be monitored independently or LDOs A, C, D, and E can be monitored collectively. The polarity of the LDOPGD pin can be set to active high or active low by bit 7 of the LDO Reset Control Register. As soon as any of the selected LDO output voltages which are monitored falls within spec, the LDO power good (LDOPGD) pin is asserted. Once the LDO output power is stable (output rises to the programmed value), a delay is initiated before the LDOPGD pin is set. The delay is programmable by bits 2 and 3 of the LDO Reset Control Register. The default delay is 100ms, and this delay can be programmed to 0, 50, 100, or 150ms.
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SC900A
POWER MANAGEMENT Applications Information (Cont.)
Active Shutdown The shutdown control bits determine how the on-chip active shutdown switches behave. Each LDO register uses bit 5 of the LDO output voltage data byte to control the shutdown behavior. When the active shutdown bit is enabled (set to 1), the capacitance on the LDO output will be discharged by an on-chip FET after the LDO is disabled. When the active shutdown bit is disabled (set to 0), the output capacitance on the LDO output is discharged by the load. The default active shutdown state for all LDOs is on. ON/OFF Control Register Each individual LDO may be turned on or off by accessing the ON/OFF control register. LDOs are turned on by setting their respective on/off bit to 1. Likewise, they can be turned off by setting the on/off bit to 0. This allows for on/off control with a single write command. If the enable (EN) pin is high and data is written to the LDO voltage registers, the LDO outputs will go to the voltage prescribed by the Output Voltage Code bits (0-4). Data will not be lost when toggling the on/off bit from 0 to 1. However, if the EN pin is forced low, all circuitry in the device is disabled. All programmed information is lost when the enable bit is subsequently pulled high. VASEL Pin The VASEL pin sets the default voltage of LDO A, the core supply. When this pin is set to VIN, the default voltage is 2.80V. When this pin is set to GND, the default voltage is 1.80V. The voltage can be changed from its default state after start up by writing to the LDO voltage code register. Device Addressing Following a start condition, the master must output the address of the slave it is accessing. The most significant six bits of the slave are the device type identifier (ID). For the SC900A this is fixed at 000100[B]. The next significant bit addresses a particular device. A system can have up to two SC900A devices on the bus. The two addresses are defined by the state of the A0 input (see Figure 1).
DEVICE TYPE IDENTIFIER 0 0 0 1 0 0 DEVICE ADDRESS
Pin A0 to GND = 0 Pin A0 to VIN = 1
When the A0 pin is tied to GND, device 1 has an address of 0 and the combination of device type ID and address is 0x08H. When the A0 pin is tied to VIN, device 2 has and address of 1 and the combination of device type ID and address is 0x09H. The last bit of the slave address defines the operation to be performed. When set to a one a read operation is selected; when set to a zero a write operation is selected. Following a start condition, the SC900A monitors the SDA line comparing the slave address being transmitted with its slave address (device type ID and state of A0 input). Upon a correct compare the SC900A outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the SC900A will execute a read or write operation. Protection Circuitry The SC900A provides protection circuitry that prevents the device from operating in an unspecified state. These include Under Voltage Lockout Protection, Over-temperature Protection and Short-circuit Protection. Under Voltage Lockout The SC900A provides an Under Voltage Lockout (UVLO) circuit to protect the device from operating in an unknown state if the input voltage supply is too low. When the battery voltage drops below the UVLO threshold, the LDOs are disabled. As the battery voltage increases above the hysteresis level, the LDOs are re-enabled into their previous states, provided ENABLE has remained high. If ENABLE goes low, the SC900A will shut down. Over Temperature Protection The SC900A provides an internal Over-temperature (OT) protection circuit that monitors the internal junction temperature. When the temperature exceeds the OT threshold, the OT protection disables all the LDO outputs. As the junction temperature drops below the hysteresis level the OT protection re-enables all the LDOs in their previous states, provided ENABLE has remained high. If ENABLE goes low, the SC900A will shut down. Short-Circuit Protection Each LDO output has short-circuit protection. If a short is applied to any output, the output voltage will drop and the output current will be limited to the short circuit current until the short is removed.
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R/W X
Figure 1 - Slave Address Structure
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SC900A
POWER MANAGEMENT Applications Information (Cont.)
Layout Considerations Layout is straightforward if you use the Gerber files on page 21 as a reference. Notice that the input voltage feed to the SC900A is on the bottom of the board and vias connect this voltage track to the top of the board and then to the SC900A itself. The input bypass can be one 4.7F capacitor, two 3.3F capacitors, three 2.2F capacitors or five 1F capacitors. The determining factor is how much copper is available on the input voltage feed track and LDO Reset Control Logic Table (Defaults are in Bold)
Register Name LDO A LDO B LDO C LDO D LDO E LDO Reset Control On/Off Control Register Register Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 LDOPGD Pin ARST Pin Reset Polarity Bit Reset Polarity Bit X X LDOPGD Monitor Logic Bits X ON/OFF Control LDO E 1 ON 0 OFF LDOPGD Delay Bits ON/OFF Control LDO D 1 ON 0 OFF ON/OFF Control LDO C 1 ON 0 OFF LDO (A) Reset Delay Bits ON/OFF Control LDO B 1 ON 0 OFF ON/OFF Control LDO A 1 ON 0 OFF Bit 7 X Bit 6 X Bit 5 Active Shutdown 1 = ON 0 = OFF Bit 4 Bit 3 Bit 2 Output Voltage Codes Table A for LDOs A & B Table B for LDOs C, D & E Bit 1 Bit 0
how much room is available. If the input voltage track is very thin, then use five 1F capacitors placed very close to the input pins of the SC900A. If the input track is fairly thick, then you can use a single 4.7F capacitor at the beginning of the voltage feed track since a wider track has less inductance per inch. The SC900AEVB has five 1F capacitors, but these can be replaced with one 4.7F in place of C1 and opens in place of C9, C14, C15, and C16 (see page 20 for details).
LDO Reset Control Logic Table (Defaults are in Bold)
Bit 7 Result Bit 6 Result Bit 5 Bit 4 Result Bit 3 Bit 2 Result Bit 1 Bit 0 ARST Delay 0 0 150ms Result LDOPGD Pin Polarity 0 High: Power Fail Low: Power Good High: Power Good Low: Power Fail ARST Pin Polarity 0 High: Reset Low: Power Good High: Power Good Low: Reset 0 LDOPGD Monitor Logic 0 LDOs A, C, D & E Good LDO E Good 0 LDOPGD Delay 0 150ms
1
1
0
1
0
1
100ms
0
1
50ms
1 1
0 1
LDO C Good LDO D Good
1 1
0 1
50ms 0ms
1 1
0 1
100ms 0ms
Note: Digital outputs are powered from INB, additionally LDOB must be on for operation of LDOPGD and ARST.
SC900A Slave Address
DEVICE TYPE IDENTIFIER 0 0 0 1 0 0 DEVICE ADDRESS A0 R/W X
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SC900A
POWER MANAGEMENT Applications Information (Cont.)
Output Voltage Code Bits: A 5-bit linear DAC controls the output voltage of each LDO. The DAC and error-amp gain are scaled so that the LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table A for the bitcodes and their corresponding voltages for LDOs A and B, and Table B for the bitcodes and corresponding voltages for LDOs C, D and E. Table A - LDO Output Voltage Control Settings for LDOs A and B
BIT 4 0 0 0 0 0 1 1 BIT 3 0 0 0 0 0 1 1 BIT 2 0 0 0 0 1 1 1 BIT 1 0 0 1 1 0 1 1 BIT 0 0 1 0 1 0 0 1 LDO Output Voltage 1.45V 1.50V 1.55V 1.60V 1.65V 2.95V 3.00V
Table B - LDO Output Voltage Control Settings for LDOs C, D and E
BIT 4 0 0 0 0 0 1 1 BIT 3 0 0 0 0 0 1 1 BIT 2 0 0 0 0 1 1 1 BIT 1 0 0 1 1 0 1 1 BIT 0 0 1 0 1 0 0 1 LDO Output Voltage 1.75V 1.80V 1.85V 1.90V 1.95V 3.25V 3.30V
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SC900A
POWER MANAGEMENT Applications Information (Cont.)
Using the I2C Interface
The SC900A is a read-write slave mode I2C device and complies with the Philips I2C standard version 2.1 dated January 2000. The SC900A has six user-accessible internal 8-bit registers. The I2C interface has been designed for program flexibility, in that once the slave address has been sent to the SC900A enabling it to be a slave transmitter/receiver, any register can be written to or read from independently of each other. While there is no auto increment/decrement capability in the SC900A I2C logic, a tight software loop can be designed to randomly access the next register independent of which register you have been accessing. The start and stop commands frame the datapacket and the repeat start condition is allowed if necessary. SC900A Limitations to the I2C Specifications Seven-bit addressing is required for communication with the SC900A; ten-bit addressing is not allowed. Any general call address will be ignored by the SC900A. Note that the SC900A is not CBUS compatible. Finally, the SC900A can operate in standard mode (100kbit/s) or fast mode (400kbit/s). Supported Formats Direct Format - Write The simplest format for an I2C write is the direct format. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900A I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8-bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P].
I2C Direct Format - Write
S
Slave Address
W A Register Address
Slave Address: 7 bit Register Address: 8 bit Data: 8 bit
A
Data
AP
S: Start Condition W: Write = `0' A: Acknowledge (sent by slave) P: Stop condition
Combined Format - Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900A I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously addressed 8-bit data byte. The master then sends a non-acknowledge (NACK). Finally the master terminates the transfer with the stop condition [P].
I2C Combined Format - Read
S
Slave Address
W A Register Address
A Sr Slave Address R
A
Data
NACK
P
S: Start Condition Slave Address: 7 bit W: Write = `0' Register Address: 8 bit R: Read = `1' Data: 8 bit A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition
(c) 2005 Semtech Corp.
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SC900A
POWER MANAGEMENT Applications Information (Cont.)
Stop Separated Reads Another read format is available which is, in effect, an extension of the combined format read. This format allows a master to set up the register address pointer for a read and return to that slave some time later to read the data. After the start condition [S], the slave address is sent, followed by a write. The SC900A I2C then acknowledges that it is being addressed, and the master responds with the 8-bit register address. The master then sends a stop or restart condition, and may address another slave. Some time later the master sends a start or restart condition, and a valid slave address is sent, followed by a read. The SC900A I2C then acknowledges and returns the data at thee register address location that had previously been set up.
I2C Stop Separated Format - Read Master Addresses other Slaves
Register Address Setup Access
Register Read Access S/Sr Slave Address A R A Data NACK P
S Slave Address W A Register Address A P S Slave Address B S: Start Condition Slave Address: 7 bit W: Write = `0' Register Address: 8 bit R: Read = `1' Data: 8 bit A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition
(c) 2005 Semtech Corp.
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SC900A
POWER MANAGEMENT Timing Diagrams
ARST and LDOPGD Timing
LDO A:
VOUTA VTH(A) VTH(A)
TRD VARST 90% VARST 10% VARST
LDO A, C, D & E:
VOUT VTH VTH
TPGD VLDOPGD 90% VLDOPGD 10% VLDOPGD
LDO On/Off Control via the I2C Interface
STOP START STOP
SCL
SDA
VLDOn
40us 300us
(c) 2005 Semtech Corp.
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SC900A
POWER MANAGEMENT Timing Diagrams (Cont.)
Default Start-up, Shutdown Timing Diagram
Enable
VREF
LDO A
LDO B
LDO C
LDO D
LDO E
ARST
LDOPGD
200us
15ms
100ms
100ms 15ms
(c) 2005 Semtech Corp.
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SC900A
POWER MANAGEMENT Typical Characteristics
Dropout Voltage (LDOA)
200 175 200 175
Dropout Voltage (LDOB-E)
Dropout Voltage (mV)
150 125
T = 25C
Dropout Voltage (mV)
T = 85C
150
T = 85C
125 100
T = 25C
100 75 50 25 0 0 25 50
T = -40C
75 50 25 0
T = -40C
Load Current (mA)
75
100
125
150
175
200
0
25
Load Current (mA)
50
75
100
125
150
Load Regulation (LDOA)
0
Load Regulation (LDOB-E)
0
VIN = 3.7V
T = -40C
VIN = 3.7V
T = -40C
Output Voltage Variation (mV)
Output Voltage Variation (mV)
-2 -4 -6
T = 85C
-2 -4 -6
T = 85C
-8
T = 25C
-8
T = 25C
-10 -12 0 25 50 75 100 125 150 175 200
-10 -12 0 25 50 75 100 125 150
Load Current (mA)
Load Current (mA)
Line Regulation (LDOA-B)
Load Current = 1mA
12 12
Line Regulation (LDOC-E)
Load Current = 1mA
Output Voltage Variation (mV)
10 8
T = 85C
Output Voltage Variation (mV)
10 8 6
T = 25C
T = 85C
6
T = 25C
4
T = -40C
4 2
T = -40C
2 0 2.7 3.2 3.7 4.2 4.7 5.2 5.7
0 2.7 3.2 3.7 4.2 4.7 5.2 5.7
Input Voltage (V) (c) 2005 Semtech Corp. 18
Input Voltage (V) www.semtech.com
SC900A
POWER MANAGEMENT
Load Transient (LDOA-E)
VIN = 3.7V, Io = 10mA to 150mA step
Line Transient (LDOA-E)
VIN = 3.7V, Io = 150mA
VO 20mV/div
VO 10mV/div
IO 100mA/div
VIN 1V/div
1ms/div
1ms/div
Output Noise v Load Current (LDOA-B)
VIN = 3.7V, VO = 3V
50 45
T = 85C
Output Noise v Load Current (LDOC-E)
VIN = 3.7V, VO = 3.3V
50 45 40
T = -40C T = 25C T = 85C
Output Voltage Noise (V)
40 35 30 25 20 0 25 50 75 100 125 150 175 200
T = -40C T = 25C
Output Voltage Noise (V)
35 30 25 20 0 25 50 75 100 125 150
Load Current (mA)
Load Current (mA)
PSRR v Frequency (LDOA-B)
0
VIN = 3.7V, VO = 3V
Power Supply Rejection (dB)
PSRR v Frequency (LDOC-E)
0 -10 -20 -30 -40 -50 -60 -70 -80
VIN = 3.7V, VO = 3.3V
Power Supply Rejection (dB)
-10 -20 -30 -40 -50 -60 -70 -80 10 100 1000 10000
10
100
1000
10000
Frequency (Hz) (c) 2005 Semtech Corp. 19
Frequency (Hz) www.semtech.com
SC900A
POWER MANAGEMENT Evaluation Board Schematic
SC900A PWR TP1
1
VIN
INA
INB
INCD
INE C16 0.1uF D1 LDOPGD
R1 150
R2 150 D2 ARST R4 7.5k R5 7.5k TP8 TP7 ARST LDOPGD
R3 0
AM1 TP2
1
C1 0.1uF
C9 0.1uF
C14 C15 0.1uF 0.1uF
J1 LDOA
J2 LDOB
J3 LDOC
J4 LDOD
J5 LDOE
Q1 FMMT3904 J7 GND J8 GND Q2 FMMT3904 TP3 SCL
VIN 13 INA 19 INB 2 INCD 17 INE 14
AM2 U1
20 1 18 16 15 11
TP4 SDA
VIN LDOA INA LDOB LDOC INB LDOD INCD LDOE INE 5 EN VREF 9 LDOPGD 10 ARST 3 SDA 4 SCL 6 A0 VASEL 12 GND DGND SC900A
C2 0.1uF
8 7
C3 2.2uF
C4 2.2uF
C5 2.2uF
C6 2.2uF
C7 2.2uF
+5V EXTERNAL J9
1 2
R7 7.5k R8 7.5k
SC900A PWR R6 100k TP5 A0 U2 R9 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
18 17 16 15 14 13 12 11 10 9
TP9 ENABLE J6
1 2
VASEL
SC900A PWR R18 SC900A PWR
C8 10uF
EXTERNAL SUPPLY SC900A PWR SW1
6 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19
TP6 VASEL SC900A PWR
SC900A PWR R10 150 R11 100k D3 ENABLE U3
1 2 3
SC900A PWR
100k (Non-use) R17 0
VDD
100k
SC900A Power Select C11 0.1uF +5V USB
R12 150 D4
R13 150 D5 USB
R14 100k
+5V R15 USB 100k
EXTERNAL
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P3.0/C2D C2CK/RST P1.0 P1.1 P1.2 VREGIN P1.3 VBUS D+ P1.4 DP1.5 P1.6 P1.7 GND C8051F320
5 4
C2DAT 1 C2CLK 2
3
J10
NC7S04
C10 0.1uF
PROGRAM & DEBUG
7 8 5 4 3
R16 150 C12 4.7uF C13 1uF D6 USB BUS
J11
1 2 3 4
F1 1A
USB
(c) 2005 Semtech Corp.
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SC900A
POWER MANAGEMENT Evaluation Board Gerbers
Top Gerber
Bottom Gerber
Top Silk Gerber
Bottom Silk Gerber
(c) 2005 Semtech Corp.
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SC900A
POWER MANAGEMENT Outline Drawing - MLPQ-20L 4 x 4
A D B
DIM
A A1 A2 b D D1 E E1 e L N aaa bbb
SEATING PLANE A1 C D1 LxN E/2 E1 2 1
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C
.031 .035 .040 .000 .001 .002 - (.008) .007 .010 .012 .153 .157 .161 .100 .106 .110 .153 .157 .161 .100 .106 .110 .020 BSC .011 .016 .020 20 .004 .004
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
0.80 0.90 1.00 0.00 0.02 0.05 - (0.20) 0.18 0.25 0.30 3.90 4.00 4.10 2.55 2.70 2.80 3.90 4.00 4.10 2.55 2.70 2.80 0.50 BSC 0.30 0.40 0.50 20 0.10 0.10
N bxN bbb e D/2 CAB
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Marking Information
Top Marking
yy = two-digit year of manufacture ww = two-digit week of manufacture
(c) 2005 Semtech Corp.
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SC900A
POWER MANAGEMENT Land Pattern - MLPQ-20L 4 x 4
K
DIMENSIONS DIM C G H K P X Y Z INCHES (.155) .122 .106 .106 .021 .010 .033 .189 MILLIMETERS (3.95) 3.10 2.70 2.70 0.50 0.25 0.85 4.80
(C)
H
G
Z
Y X P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 FAX (805)498-3804
(c) 2005 Semtech Corp.
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